For effective platform level testing of computer system, one of the elements to be addressed is the testing of memory devices. The continuing increase in speeds of operation in computer platforms of devices has resulted in certain complications such that conventional testing of memory may no longer provide adequate results.
Because cost considerations for test implementation, including the cost of including additional TAP pins for testing, DRAM (Dynamic Random Access Memory) logic commonly does not incorporate typical board testing logic. In lieu of such test access, original equipment manufacturers (OEMs) implement testing processes that include sending functional traffic to memory devices at low speeds, and relying upon the board testing apparatus from the CPU (central processing unit) to provide for testing operation.
However, with the increasing DDR (Double Data Rate) speeds and varying vendor proprietary logic implementations, certain DRAM devices do not respond reliably to this conventional means of testing at low speeds, and thus require other means for providing board testing of memory.